AI circuit design software for electrical engineers
Circuit design that verifies itself.
Pulse drafts the schematic, pulls real parts, drives your SPICE simulator, and refuses to call a design done until every spec passes. It runs on your machine and lives alongside the EDA tools your team already uses.
| check | condition | measured | limit | verdict |
|---|---|---|---|---|
| vout_dc | steady, 3 A | 3.302 V | 3.30 ± 1 % | pass |
| ripple_pp | steady, 3 A, C derated | 8.7 mV | ≤ 33 mV | pass |
| step_undershoot | 0.5 → 3 A, 1 A/µs | 71 mV | ≤ 99 mV | pass |
| efficiency | 3 A, 25 °C | 92.4 % | ≥ 90 % | pass |
| phase_margin | ac, fc = 62 kHz | 58° | ≥ 45° | pass |
| mc_yield | 500 runs, ± tol | 99.4 % | ≥ 99 % | pass |
Design
From a spec to a schematic with real parts
Describe the circuit and its constraints. Pulse drafts a schematic, searches DigiKey for parts that are actually in stock, and builds SPICE models from their datasheets, with the page it used cited on the part.
Verify
Test benches, sweeps, and a gate that cannot be talked past
Spec checks are declared before any result exists. Pulse generates the benches, runs ngspice or LTspice, and evaluates PASS or FAIL in the engine. A failing check sends the design back for another revision, not to a chat window.
Fit in
Inside the EDA tools you already use
KiCad schematics come in and go out with fidelity reporting on every construct. Altium, OrCAD, and Cadence are on the roadmap. Nothing about your flow has to change to try it.
How a design converges
- 1Contract. You approve the tolerance table before anything is drawn.
- 2Draft. The agent emits a circuit and attaches sourced parts with datasheet-derived SPICE models.
- 3Simulate. Transient, AC, parameter sweeps, and Monte Carlo run locally in your simulator.
- 4Check. The engine grades each spec. Failures come back with the measured number and the limit.
- 5Revise. The agent changes the design, not the story, and re-runs until the gate passes.
- 6Export. You approve the write to KiCad. Every run stays in a provenance ledger you can audit.
What teams verify with Pulse
Power stages, analog front ends, signal chains, and interfaces
Power electronics
Buck, boost, and LDO stages with load-step, ripple, efficiency, and loop-stability checks. Gate drive and bootstrap sizing against real FET models.
Analog front ends
Instrumentation amplifiers, active filters, ADC drivers, and sensor conditioning with noise, bandwidth, and settling verified across component tolerances.
Signal chains
Op-amp stages, comparators, references, and level shifters checked for offset, gain error, slew, and phase margin before a board is ever ordered.
Interfaces and protection
RS-485, CAN, and USB front ends with TVS and series-element choices validated for clamp voltage, insertion loss, and surge margin.
Privacy
Built for teams that cannot send their schematics anywhere
- All circuit and project data stays on the machine. Only chat messages and structured tool results leave, and only to the model provider you choose.
- Run it against a self-hosted instance on open models, or against zero-data-retention APIs.
- A network ledger records every host the install has ever contacted. There is no third-party telemetry.
- API keys live in an owner-only file on disk, never in config, logs, or checkpoints.
Team
Two engineers who have used every one of these tools in anger
Pulse is built by Jake Li and Mena Filfil, both MIT graduates in Electrical Engineering and Computer Science. Jake is completing an MEng at MIT's Radius Lab working on on-chip passives. Mena is a Forward Deployed Engineer at xAI working on applied AI for government. Between us: SpaceX, Palantir, Nominal, and daily time in LTspice, Cadence, Altium, and KiCad.
The first version of Pulse took first place in the Circuits Track at the MIT MTL 2026 Hackathon.
Questions engineers ask first
- Does Pulse replace KiCad, Altium, or LTspice?
- No. Pulse is a companion that reads and writes the schematic formats your team already uses. KiCad round-trips today with a fidelity report on every construct; Altium, OrCAD, and Cadence are next. Your simulator stays your simulator.
- How does Pulse avoid hallucinated simulation results?
- The language model never sees raw simulator logs or waveform tables. Spec checks are declared before a run exists, ngspice or LTspice produces the numbers, and the Pulse engine computes PASS or FAIL. The model only sees structured, capped results and cannot grade its own work.
- Which circuit simulators are supported?
- ngspice ships with Pulse as a bundled sidecar, so it works out of the box. LTspice is supported where installed. Transient, AC, DC sweep, parameter sweeps, and Monte Carlo analyses are driven automatically from the spec.
- Where do parts and SPICE models come from?
- Pulse searches DigiKey for in-stock parts that meet the constraint, then fits SPICE models from the manufacturer datasheet and cites the section and figure it used, so a reviewer can check the model against the source.
- What leaves our network?
- Only the chat messages and structured tool results needed for the model to reason. Schematics, netlists, waveforms, and project files stay local. You can point Pulse at a self-hosted model or a zero-data-retention API, and the built-in network ledger shows every host contacted.
- Can we try it?
- Yes, through a private evaluation on one of your own circuits. There is no public download or demo while the product is pre-release. Use the form below and we will set one up.
Request access
Tell us what you are designing
We run private evaluations with engineering teams on their own circuits. There is no public demo. Send a note and one of us will reply within two business days.